How Does Junction Field Effect Transistor (JFET) Work | A Comprehensive Lecture

In the lecture of Bipolar Junction Transistor (BJT) , we learned that in BJT we control output current (collector current) with input current (base current). A small change in base current makes a huge change in collector current.

Working principle of an Field Effect Transistor

FET is a transistor in which current is controlled by varying the resistance of the channel from where the current is passing. The resistance is controlled by electric field.

Type of Field Effect Transistor

Depending upon the construction. FET is divided into two categories

1. Junction Field Effect Transistor (JFET)
2. Metal-Oxide Field Effect Transistor (MOSFET)

What is Junction Field Effect Transistor?

Just like BJT, JFET is also a three terminal device. But in the case of JFET we control current with the help of electric field generated around the reverse bias depletion region of PN junction. In other words the effective resistance can be increased or decreased by controlling the depletion region.

In the following lecture we will discuss JFET and its characteristics.

Construction of JFET

To understand the operation of JFET, it is necessary to understand the mechanism of current flow inside JFET. The JFET has three terminals called source (S), drain (D) and gate (G).

There are two types of JFET

1. N channel JFET
2. P channel JFET

Fig-1 shows the source and drain are connected to the two ends of n-channel and p-channel JFETs. Two p-type regions are diffused into n-type region to make a channel between them. Similarly two n-type regions are diffused into p-type region to form a p-channel. The gate lead is connected to the diffused regions.

Fig-1: JFET Types

JFET Symbol

The following are the JFET schematic symbols for n channel and p channel types

Fig-2: n-channel JFET symbol and p-channel JFET symbol

JFET Working Principle:

JFET operation basically depends upon the potential difference between gate and source. The reverse bias voltage between the gate and the source changes the width of the depletion region. As a result, the width of the channel shortens or expands and hence current passing through the channel decreases or increases respectively.

The following explanation will guide you actually how JFET works. There are two possibilities of VGS (gate-source voltage).

First Condition when VGS= 0

When VGS is equal to zero its mean the gate and the source are at the same potential. (See Fig-3)

Fig-3: JFET Operation when VGS = 0

You can observe in the above figure source is grounded and 0V is applied at the gate. It’s obvious that both p-type regions are connected with the gate but here for simplicity we consider that gate lead is attached to only one p-type region. VDD is the voltage applied between the drain and the source. The drain is at the higher potential and the source is at the lower potential.

The potential difference between the gate and the drain is higher as compared to the gate and the source. So the depletion region will expand more towards the drain and then will contract towards the source.

When electrons will move from the source to the drain they will find a narrow path between the two p-type regions. Its mean by expanding the depletion region, the resistance of the channel between p-type regions has increased. So less current will flow from the drain to the source. And the drain current (ID) is equal to the source current (IS).

The same concept is applicable to p-channel JFET. But here negative voltage is applied at the drain.

Second Condition When VGS < 0

Remember JFET is always operated through the gate and the source. Now apply the negative pulse on the gate. After this pn-junction is reverse biased and spreads towards the n-channel. The result is almost similar when we applied 0V at the gate and VDD was variable.

So if you keep on increasing VGS. The depletion region will increase. The resistance of the channel will increase and hence the current will reduce. (See Fig-4)

Fig-4: Working of JFET when VGS< 0

What is Pinch Off Voltage (Vpin) in JFET?

When you keep on increasing VDD in above figures. The depletion region will spread more and more due to the increase in potential difference between the gate and the drain. A value of the VDD will come after that the current will become constant. It means after this point when you increase more VDD, the current will not change. Now the JFET has gone into saturation mode. The voltage at which JFET goes into saturation mode is known as a pinch off voltage of JFET.

To understand this concept let us draw characteristic curve by shorting the gate with the source i.e VGS = 0 as in fig-1.

Fig-5: Pinch Off Voltage of JFET

Before the pinch off voltage point, when you Increase VDD the drain current also increases. Because depletion region is not large enough. It does not have a significant impact on the ID. This is the Ohmic region or linear region. After the pinch off voltage constant current flows. Means JFET is now in saturation region.

Although the two depletion regions do not meet each other because of opposite electrostatic forces between them. But remember when we discussed reverse bias mode of pn junction and the zener diode. We discussed that every depletion region has a limit. If you keep on increasing the reverse voltage, not only depletion region will go on increasing but a voltage will come when depletion region will become short what and pn junction will go into to breakdown region.

Same is the case here. At the breakdown voltage very high drain current (ID) will pass through JFET. JFET can go into breakdown region which can bring irreversible damage to the electronic device. So it is always operated between Vpin and breakdown voltage.

What is Cutoff Voltage (VGS(OFF)) of JFET?

This is the voltage where JFET completely blocks the drain current i.e ID = 0. When VGS becomes more and more negative the depletion region spreads. A voltage level or potential difference reaches when JFET stops ID. Because the two depletion regions never meet each other due to electrostatic forces as we discussed above. To understand this consider the following curves in fig-3.

Fig-6: JFET Cutoff Voltage

Now these curves will give you more clear concept about Vpin and VGS(OFF). You can observe the cut off voltage is equal and opposite in magnitude to VDD. i.e VGS=-5. And one thing is more clear that at the Vpin the ID becomes constant whereas at VGS(OFF) the ID is zero.

What is Transconductance of JFET?

Transconductance basically shows relationship between change in output current with respect to the change in input voltage of an active device. As you have learned above that a range of VGS varies ID from saturation to cut off. So the relationship between these two is very important to understand the working of JFET. This relationship can be explained using the transconductance curve. (See Fig-7)

Fig-7: Transconductance Curve

The forward transconductance (gm) is an important parameter in the study of JFET amplifier. It can be expressed as the ratio of change in drain current to the gate-to-source voltage. Its unit is siemens

Why JFET is called square law device?

You can draw transconductance curve for any value of VGS, IDSS and VGS(OFF) by using the following Shockley’s equation

As you can observe there is a square over the input voltage values. A square law device is that which produces output equal to the square of its input. You can observe JFET also producing output approximately equal to the square of input. That is why JFET as well MOSFET are known as square law devices.

Biasing of JFET

The purpose of JFET biasing is to select proper VGS so that you can get the required ID. There are three types of biasing of JFET

1. Self Bias
2. Voltage Divider Bias
3. Current Source Bias

Self Bias JFET

Whatever we discussed above about the working of JFET. That is basically on the basis of self bias where VGS = 0 or VGS < 0 to make the pn-junction reverse bias. This is the most common type of JFET biasing.

Fig-8: Self Biased JFET

The source current passing through the resistance RS produces a voltage drop VS = ISRS whereas IS = ID.

so

Similarly a voltage drop VD produces at RD which can be found as below

So voltage between drain to source equals

Voltage Divider Bias JFET

JFET Voltage divider bias circuit is given below

Fig-9: Voltage Divider Bias for JFET

Now the voltage at the gate depends upon RG and R4. So using potential divider method we can find VG as

And the expression from ID is below

 

Constant Current Bias of JFET

Constant current biasing method is used to make ID completely independent of VGS. This can be done by connecting source of JFET with a constant current source device. (See Fig-7)

Fig-10: Constant Current Bias JFET

A BJT is connected in series. Which is a constant current device when used in saturation mode. If VEE is much much larger than VBE, then almost constant current flows through the transistor.

JFET is unipolar or bipolar?

You know that current in a diode is due to electrons and holes. Similar is the case of BJT where current flows due to holes and electrons. But in JFET there is only one type of region for current to flow either p-channel or n-channel. So at a time only one type of current passes through JFET. Either electronic current or hole current. Hence JFET is a unipolar device.

Why JFET is called voltage variable resistor?

As we have discussed above that with the increase in VGS, the depletion region goes on increasing. Which further shrinks the channel. So resistance increases or decreases by varying the voltage. That is why it is called voltage variable resistor.

Why JFET is voltage controlled device?

You can observe by varying the voltage we can control the drain current. Or in other words we can control the output of the JFET. that is why it is called voltage controlled device.

Advantages and Disadvantages of JFET

Advantages of JFET

1. As it’s a unipolar device so no electron hole recombination is needed to flow the current. Hence less noise as compared to diode and BJT.
2. Very small in size
3. Its input impedance is very high. Because both junctions are reverse biased which stops the current flow through the gate terminal.
4. JFETs have negative temperature coefficient. When the temperature increases, the majority carriers in the drain current recombine with thermally generated minority carriers, this reduces the overall drain current.
5. More resistive to radiation
6. Consume less power

Disadvantages of JFET

1. It has low gain-bandwidth product due to which they are less usable in amplifiers as compared to BJT.
2. Due to internal junction capacitance, switching speed is low as compared to BJT